The initial block also is usually used only in test benches. So anything that we need to initialize should go here. As its name suggests, this block will be executed only once at time t = 0. We have to find some other way if the delay needed in our design when we synthesize the code. Remember that # symbol is not a synthesizable element. So the always block executes always, and inside the block, “clock” is inverted continuously so that the waveform on clock looks like a square wave. The symbol # is a way to specify a delay in Verilog. In the “always” block the reg “clock” is inverted after every one-time unit delay. I’ll discuss this in detail in later chapters. But for this simulation, the simplest form of “always” should suffice. In real-world designs, “always” blocks are a little more complicated with sensitivity lists, etc…. As the name implies, “always” block will keep on executing as long as the simulation is running. The “always” block is something worth special mention here. The result should appear on the wire “out” in the simulation. The wire “out” is connected to the output port (port B) of myModule.
We will create a clock on reg “clock” by periodically inverting it and feed it to the input (port A) of myModule. I have created a wire named “out” and a reg named “clock”. The test bench is just another module, with no I/O ports as I mentioned earlier. But when it comes to implementation on real FPGA, the “top module” can have I/O ports and test benches won’t be the top modules there (we will talk about this in detail later). During the simulation, the test bench should be a “top module” (top-level module) with no I/O ports.
A test bench is nothing but another Verilog module that generates some signals and feeds it to the module under test. In order to simulate the module, we need to give some input to the module, how we do that? The answer is, we need to create a test bench! The test bench will generate the necessary inputs for the module under analysis (Here “myModule”). Ok, we have a module and tools ready now, let’s try to run a simulation on the module and see if it works as expected.